A 6-bit arbitrary digital noise emulator in 65nm CMOS technology

An arbitrary noise generator (ANG) is based on time-series charging of divided parasitic capacitance (TSDPC) and emulates power supply noise generation in a CMOS digital circuit. A prototype ANG incorporates an array of 32 times 32 6-bit TSDPC cells along with a 128-word vector memory and occupies 2...

Full description

Saved in:
Bibliographic Details
Main Authors: Matsuno, T., Fujimoto, D., Kosaka, D., Hamanishi, N., Tanabe, K., Shiochi, M., Nagata, M.
Format: Conference Proceeding
Language:English
Subjects:
Circuit noise
CMOS digital integrated circuits
CMOS memory circuits
CMOS technology
Digital circuits
Logic arrays
Noise generators
Parasitic capacitance
Power generation
Power supplies
Online Access:Request full text
Tags: Add Tag
No Tags, Be the first to tag this record!