New electromigration validation: Via Node Vector Method

• Main Authors: Young-Joon Park, Jain, P, Krishnan, S
• Format: Conference Proceeding
• Language: English
• Subjects: Analog circuits; circuit electromigration; Current density; Design automation; Electromigration; electromigration check; electromigration interaction; Frequency; Integrated circuit interconnections; Physics; Process design; System-on-a-chip; Wire
• ISSN: 1541-7026; 1938-1891
• DOI: 10.1109/IRPS.2010.5488746

Electromigration (EM) is a traditional reliability concern, aggravated recently due to intense shrinking of wire sizes and the increase in the number of interconnections on a system-on-chip (SoC). Thereby, it challenges the state-of-the-art in design, physics, process and CAD processes. To that regard, we propose a new EM check method named Via Node Vector method. The conventional EM check ignores the lead EM interaction in circuits and only checks the local current densities. The new method addresses the EM interactions and checks the EM reliability at the lead connection sites (called via node). It converts the electrical current density of each lead into an effective current density for the EM interaction consideration. For this, we introduce three new factors: length (FL), width (FW), and interaction (FB). The effective current density divergence at a via node is derived as an addition of the effective current densities of all the interacting leads, which is a close proxy to represent the physical atomic flux divergence at the via node. This divergence at a via node can then be readily compared with the technology EM spec. The proposed method is successfully applied to 28nm node IPs and shows up to ~4X higher safe operating frequency than the conventional method allows. Additionally, it successfully identifies risky sites missed by conventional check. The Via Node Vector Method will provide higher performance with reliability in designing advanced digital and analog circuits.