Investigation of DPA Resistance of Block RAMs in Cryptographic Implementations on FPGAs

• Main Authors: Shah, Shaunak, Velegalati, Rajesh, Kaps, Jens-Peter, Hwang, David
• Format: Conference Proceeding
• Language: English
• Subjects: Block RAM; Correlation; Cryptography; Differential Power Analysis; Field programmable gate arrays; Power demand; Random access memory; SDDL; Security; Side Channel Analysis; Synchronization; Table lookup; Xilinx FPGA
• ISSN: 2325-6532; 2640-0472
• DOI: 10.1109/ReConFig.2010.80

Security at low cost is an important factor for cryptographic hardware implementations. Unfortunately, the security of cryptographic implementations is threatened by Side Channel Analysis (SCA). SCA attempts to discover the secret key of a device by exploiting implementation characteristics and bypassing the algorithm's mathematical security. Differential Power Analysis (DPA) is a type of SCA, which exploits the device's power consumption characteristics. Several countermeasures to DPA have been proposed, however, all of them increase security at the cost of increased area which in-turn leads to increased power consumption and reduced throughput. FPGAs are popular due to their reconfigurability, lower development cost, off-the-shelf availability and shorter time to market. Block RAMs (BRAM) are large memories in FPGAs that are commonly used as ROM, FIFO, Look-up tables, etc. In this paper we explore the DPA resistance of BRAMs in Xilinx FPGAs and verify if their usage can improve the security. The results of our Advanced Encryption Standard (AES) implementations show that using BRAMs alone can improve the security over a look-up table (LUT) only design 9 times. Applying Separated Dynamic Differential Logic (SDDL) for FPGAs, a countermeasure against DPA, to this design doubles the security again leading to an 18 fold increase over the unprotected LUT design.