Application of numerical analysis to the reliability assessment of a novel package on package (PoP) structure for memory stacking

• Main Authors: Kuo-Shu Kao, Sheng-Tsai Wu, Yin-Po Hung, Tao-Chih Chang, Ren-Shin Cheng, Tai-Hong Chen
• Format: Conference Proceeding
• Language: English
• Subjects: Copper; Plastics; Random access memory; Reliability; Strain; Stress; Substrates
• ISSN: 2150-5934; 2150-5942
• DOI: 10.1109/IMPACT.2010.5699573

In order to meet the demands for the high-density, high-performance, high-speed, smaller form factor and multi-function integration in portable electronic products, novel packaging technology now trends toward system in package (SiP) technology. 3D packaging technology is one of the most optimum means to achieve SiP. The embedded technology is one of the 3D packaging solutions and playing a key role to carry out the integration of heterogeneous devices. The embedded packaging technology addressed in this study was to bond an active device on a carrier substrate and then to achieve the "active embedded" package by laminating a dielectric material such as ABF on the substrate. The active embedded technology was successfully used to replace w-BGA to package a DDR2 device in ITRI [Ko et al.]. In the previous study, a real DDR2 IC with a thickness of 50 um was chosen to carry out ITRI's active embedded technology by wafer thinning, die bonding, ABF lamination, laser-via forming and electroplating via filling [IWLPC]. For simplifying the process flow, a new stackable embedding technology is developed to form a PoP module to extend the capacity of memory. In order to learn the reliability issues induced by the CTE mismatch of materials under temperature cyclic test, a simulation model was built-up to study the thermomechanical and stress concentration behaviors of the PoP module under TCT and to predict the life cycle times of the solder joints in the PoP module. The reliability characteristics of those two different interconnection structures would be assessed and compared. The embedded DRAM package devices had been accomplished and all samples had passed LV-3 pre-condition, TCT and THST reliability test. The thermal analysis of the stacking embedded DRAM package has been investigated using finite element modeling. Regarding the solder ball, the maximum Von Mises stress and plastic strain are located at outmost corner in the first solder. The fatigue lifetime of the maximum plastic strain solder is predicted as 1223 cycles. On the other hand, the Von Mises stress of the copper via in the ABF layer was larger than that in the substrate layer, indicating a possible failure site inside the package.