Failure analysis using LVP for tolerant design about BEOL parasitic effects in nanoscale technology

• Main Authors: Jung-Tae Kim, Yong-Seop Kim, Moo-Jong Hong, Yun-Woo Lee, Eun-Chul Lee, Gab-Soo Han
• Format: Conference Proceeding
• Language: English
• Subjects: Clocks; Crosstalk; Delay; Failure analysis; Flip-flops; Very large scale integration
• ISSN: 1946-1542; 1946-1550
• DOI: 10.1109/IPFA.2011.5992755

In nanoscale technology, parasitic effects by Backend of line (BEOL) according to feature sizes shrinkage have been reported as main issue of chip failure in VLSI designs. The timing defect failure and signal integrity problem such as crosstalk occur most frequently in deep submicron technologies. However, the root causes of timing defect and signal integrity problem are very difficult to diagnose in comparison with other stuck defects because they can be changed by external factors. This paper presents an efficient failure analysis method for initial yield ramp up and ongoing product with laser voltage probing (LVP) technology. We also describe several case studies on the failure analysis for design error improvement and yield enhancement. First, we identified the root cause of SCAN hold time failure at high voltage. In particular, several signal paths lead to unexpected timing defect failure such as crosstalk delay. Next, a crosstalk switch failure is defined as coupled interference from signal lines to a logically unrelated signal line. We analyzed failure of e-fuse data affected by BEOL crosstalk noise. The failure phenomenon is irregularly caused by test patterns, layout of signal line and applied voltage. In this paper, our FA results are contributed to providing guides for tolerant design about BEOL parasitic effects in nanoscale technology.