High-Performance and Scalable System Architecture for the Real-Time Estimation of Generalized Laguerre-Volterra MIMO Model From Neural Population Spiking Activity

• Published in: IEEE journal on emerging and selected topics in circuits and systems 2011-12, Vol.1 (4), p.489-501
• Main Authors: Li, Will X. Y., Chan, Rosa H. M., Zhang, Wei, Cheung, Ray C. C., Song, Dong, Berger, Theodore W.
• Format: Article
• Language: English
• Subjects: Algorithm design and analysis; Brain modeling; Computational modeling; Field programmable gate array (FPGA); Field programmable gate arrays; generalized Laguerre-Volterra model; Hardware; IP library; Kernel; MIMO; multiple-input multiple-output (MIMO) system; neuroscience
• ISSN: 2156-3357; 2156-3365
• DOI: 10.1109/JETCAS.2011.2178733

A hardware-based computational platform is developed to model the generalized Laguerre-Volterra (GLV) multiple-input multiple-output (MIMO) system which is essential in identification of the time-varying neural dynamics underlying spike activities. Time cost for model parameters estimation is greatly reduced by a significant enhancement of 3.1 \,\times 10^{3}~{\rm x} in data throughput of the Xilinx XC6VSX475T field programmable gate array (FPGA)-based system compared to a C model running on an Intel i7-860 Quad Core processor. The processing core consists of a first stage containing a vector convolution and MAC (multiply and accumulation) component; a second stage containing a prethreshold potential updating unit with an error approximation function component; and a third stage consisting of a gradient calculation unit. The hardware platform is scalable with the utilization of different number of processing units within each stage. It is also easily extendable into a multi-FPGA structure to further enhance the computational capability. A hardware IP library is proposed for versatile neural models and applications. The implementation of the self-reconfiguring platform and its applications to future research of neural dynamics are explored.