MCFQ: Leveraging Memory-level Parallelism and Application's Cache Friendliness for Efficient Management of Quasi-partitioned Last-level Caches

To achieve high efficiency and prevent destructive interference among multiple divergent workloads, the last-level cache of Chip Multiprocessors has to be carefully managed. Previously proposed cache management schemes suffer from inefficient cache capacity utilization, by either focusing on improvi...

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Bibliographic Details
Main Authors: Kaseridis, D., Iqbal, M. F., Stuecheli, J., John, L. K.
Format: Conference Proceeding
Language:English
Subjects:
Benchmark testing
Fitting
Interference
Parallel architectures
Resource management
Sensitivity
Throughput
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Summary:To achieve high efficiency and prevent destructive interference among multiple divergent workloads, the last-level cache of Chip Multiprocessors has to be carefully managed. Previously proposed cache management schemes suffer from inefficient cache capacity utilization, by either focusing on improving the absolute number of cache misses or by allocating cache capacity without taking into consideration the applications' memory sharing characteristics. In this work we propose a quasi-partitioning scheme for last-level caches, MCFQ, that combines the memory-level parallelism, cache friendliness and interference sensitivity of competing applications, to efficiently manage the shared cache capacity. The proposed scheme improves both system throughput and execution fairness -- outperforming previous schemes that are oblivious to applications' memory behavior. Our detailed, full-system simulations showed an average improvement of 10% in throughput and 9% in fairness over the next best scheme for a 4-core CMP system.
ISSN:1089-795X
2641-7944
DOI:10.1109/PACT.2011.74