A 16 MHz BW 75 dB DR CT \Delta\Sigma ADC Compensated for More Than One Cycle Excess Loop Delay

• Published in: IEEE journal of solid-state circuits 2012-08, Vol.47 (8), p.1884-1895
• Main Authors: Singh, V., Krishnapura, N., Pavan, S., Vigraham, B., Behera, D., Nigania, N.
• Format: Article
• Language: English
• Subjects: Analog-to-digital converter (ADC); Ash; compensation; continuous-time; Delay; delta-sigma; excess loop delay (ELD); Feedforward neural networks; Modulation; Noise; oversampling; Quantization; quantizer; sample and hold (S/H); Transfer functions
• ISSN: 0018-9200; 1558-173X
• DOI: 10.1109/JSSC.2012.2196730

The maximum sampling rate of a continuous-time ΔΣ modulator in a given process is limited by the minimum flash ADC delay that can be realized. Excess loop delay compensation techniques that are widely used can compensate for delays up to half a clock cycle. Addition of a fast loop outside the flash ADC can break this limit and compensate for one and half clock cycles of delay at the cost of reducing the order of noise shaping by one. This technique, along with a low latency flash ADC, and a delay free calibrated DAC, result in a lowpass continuous-time ΔΣ ADC with the highest reported sampling rate in a 0.18 m process. The prototype occupies 0.68 mm 2 , consumes 47.6 mW, and operates at 800 MS/s. In a 16 MHz bandwidth (oversampling ratio of 25), the dynamic range, maximum signal to noise ratio, and maximum signal to noise and distortion ratios are 75 dB, 67 dB, and 65 dB respectively. In a 32 MHz bandwidth, the dynamic range, maximum signal to noise ratio, and maximum signal to noise and distortion ratios are 64 dB, 57 dB, and 57 dB, respectively.