Accurate electrical simulation and design optimization for silicon interposer considering the MOS effect and eddy currents in the silicon substrate

• Main Authors: Jing Zhou, Lixi Wan, Fengwei Dai, Huijuan Wang, Chongshen Song, Tianmin Du, Yanbiao Chu, Maoyun Pan, Guidotti, D., Liqiang Cao, Daquan Yu
• Format: Conference Proceeding
• Language: English
• Subjects: Insertion loss; Permittivity measurement; Power transmission lines; Silicon; Substrates; Through-silicon vias; Transmission line measurements
• ISSN: 0569-5503; 2377-5726
• DOI: 10.1109/ECTC.2012.6248902

In this paper, a group of coplanar lines on a silicon dioxide insulating layer on a nominally doped silicon substrate is simulated and measured. Electrical parameters extracted from published data are used and lead to substantially improved agreement with measurements. In addition, several models of redistribution layer (RDL) with different shape-TSVs (through silicon vias) are simulated, along with two different joint structures between TSV and RDL. Simulation result suggest that because the electrical length is very short reflection losses attributed to the structural details of the TSV may be ignored in the applicable frequency band of the TSV. In addition, several optimized transmission line structures are designed and simulated. Results suggest that design criteria used to optimize lines in organic substrates are not directly transferable to a silicon substrate. This paper shows a simple but effective method with which to analyze the influences exerted by the metal oxide semiconductor (MOS) capacitance at the TSV interface and eddy currents in the substrate on a transmission line. Finally, newly de-embedded test structures are provided to extract spice model parameters for TSV modeling.