Virtual Floating-Point Units for Low-Power Embedded Processors

Floating-point (FP) arithmetic is becoming increasingly common in many embedded applications. Typically these applications execute in battery-powered, energy-constrained environments. Due to their tight area and power constraints, however, embedded processors often do not incorporate dedicated FP ha...

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Bibliographic Details
Main Authors: Gilani, S. Z., Nam Sung Kim, Schulte, M.
Format: Conference Proceeding
Language:English
Subjects:
DSP
Flip-flops
floating-point
Hardware
Hazards
low-power
Pipelines
Program processors
Vectors
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Summary:Floating-point (FP) arithmetic is becoming increasingly common in many embedded applications. Typically these applications execute in battery-powered, energy-constrained environments. Due to their tight area and power constraints, however, embedded processors often do not incorporate dedicated FP hardware. Instead, they only support fixed-point (FxP) arithmetic at the expense of considerably increased programming complexity and longer runtimes. In this paper, we propose low-overhead approaches to support FP arithmetic (addition, subtraction, multiplication, fused multiply-add) without incurring the high area and power penalties of dedicated FP hardware. Our approaches utilize the existing FxP execution resources in processors plus a small amount of additional hardware to support FP operations. Compared to a baseline processor with dedicated FP hardware, a processor with our approaches can reduce the area and power consumption by 24% and 31%, respectively. We also demonstrate that a processor using our approaches improves energy efficiency and performance by nearly 30%.
ISSN:1063-6862
DOI:10.1109/ASAP.2012.28