Asynchronous and synchronous implementations of the autocorrelation function for the FPGA X-ray pixel array detector

• Main Authors: Hromalik, M. S., Green, K., Philipp, H., Tate, M. W., Gruner, S. M.
• Format: Conference Proceeding
• Language: English
• Subjects: Application specific integrated circuits; Delay; Detectors; Field programmable gate arrays; Latches; Photonics; Prototypes
• DOI: 10.1109/RTC.2012.6418381

The design of the FPGA Pixel Array Detector (PAD) prototype and initial experimental results of real-time implementations of its autocorrelation function are presented. This is a pixelated 2D silicon device for detecting X-rays in X-ray Diffraction Experiments and is comprised of three layers: the diode detection and ASIC analog electronics layers connected by a massively parallel interface to a third FPGA layer consisting of a Xilinx XC6VLX550T device. A high-speed labor intensive asynchronous interface as well as a more traditional synchronous interface will be presented. Traditionally X-ray PADs have been application-specific as their functionality is built into the ASIC layer. In the FPGA PAD, however, the ASIC layer consists of a simple photon counting front end with a single-bit digitized output to the FPGA layer. As most of the functionality is migrated to the FPGA layer, the reconfigurability of the FPGA allows for great flexibility in terms of detector applications. The massively parallel connection between the ASIC layer and the FPGA layer also allows for data-flow implementations of detector algorithms on the parallel input bit array. Real-time data processing realizes lower data transfer rates to offline storage and higher time-resolution during experiments. An example application of a real-time autocorrelation function (ACF) for X-ray Photon Correlation Spectroscopy (XPCS) experiments is also described for a prototype of the FPGA PAD. Both a synchronous implementation and a very high-speed Region of Interest asynchronous implementation were designed. A time resolution range of 100ns to 1s was achieved for the synchronous implementation and a maximum resolution down to 36ns was realized for the Asynchronous Implementation. The required data transfer rate was also reduced from 2.56 Gb/s to 4.4Mb/s over the entire array.