Scalable matrix multiplication algorithm for IRAM architecture machine

A scalable bit matrix machine model was proposed by us previously (G. Vesztergombi et al., 1997). Now we extend this IRAM type model for numerical calculations. The k digit numbers are represented in a bit parallel way, thus the number of rows in the memory is scaled up correspondingly, which means...

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Bibliographic Details
Main Authors: Vesztergombi, G., Odor, G., Rohrbach, F., Varga, G.
Format: Conference Proceeding
Language:English
Subjects:
Centralized control
Chemical technology
Communication system control
Computational intelligence
Computer architecture
Distributed processing
Emulation
Machine intelligence
Materials science and technology
Numerical models
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Summary:A scalable bit matrix machine model was proposed by us previously (G. Vesztergombi et al., 1997). Now we extend this IRAM type model for numerical calculations. The k digit numbers are represented in a bit parallel way, thus the number of rows in the memory is scaled up correspondingly, which means that the number of 1 bit CPUs is also increased proportionally. Still relying on the simple string communication interprocessor network, we prove that loading and multiplication of n/spl times/n matrices are executable in O(n) time. Speed estimates are calculated using emulation on the 8192 processor CERN-ASTRA machine.
DOI:10.1109/EMPDP.1998.647221