A low-power 1GHz razor FIR accelerator with time-borrow tracking pipeline and approximate error correction in 65nm CMOS

• Main Authors: Whatmough, P. N., Das, S., Bull, D. M.
• Format: Conference Proceeding
• Language: English
• Subjects: Clocks; Digital signal processing; Error correction; Finite impulse response filters; Latches; Pipelines; Timing
• ISSN: 0193-6530; 2376-8606
• DOI: 10.1109/ISSCC.2013.6487800

The unrelenting demands of wireless/multimedia DSP workloads necessitate specialized hardware to achieve higher performance and power efficiency. Razor systems offer even greater power efficiency by minimizing static supply voltage (V DD ) guardbands for process/voltage/temperature (PVT) variation, while also providing a degree of resilience to general delay faults (e.g. SEUs). To date, Razor has only been demonstrated on silicon in the context of microprocessor pipelines [1][2]. Reported Algorithmic Noise Tolerance (ANT) circuits [3][4] operate at very high error rates, but rely on imbalanced ripple-carry adders and hence clock frequency (F clk ) is limited (50-88MHz). ANT also requires additional datapaths for error detection/correction, which cannot be clock gated in the absence of errors, increasing baseline area and power. Combining Razor error detection with algorithm-level correction enables high-F clk datapaths and low-overheads. A 0.19mm 2 16-tap Razor FIR datapath is fabricated in 65nm LP CMOS, with input and output SRAMs, tunable pulse-clock generator, BIST logic and an AHB slave on-chip bus interface (Fig. 24.5.1), demonstrating: 1) two distinct fixed-latency Razor error-correction techniques for real-time DSP datapaths: time-borrow tracking (TBT) and interpolation-based approximate error correction (AEC); 2) a Razor latch (RZL) circuit with reduced pessimism; 3) a 1GHz datapath, an order of magnitude improvement over [3][4] due to elimination of ripple-carry adders; 4) energy efficiency improvement of up to 37%.