On the drop impact performance of IPDTM devices with different process technologies

• Main Authors: Yiyi Ma, Kim-Yong Goh, Xueren Zhang, Wei-Zhen Goh
• Format: Conference Proceeding
• Language: English
• ISSN: 1089-8190; 2576-9626
• DOI: 10.1109/IEMT.2012.6521790

The associated significant loss with passive devices on silicon substrate is generally believed to be responsible for the presence of low quality factors, making it a poor candidate for the design of efficient output matching networks. STMicroelectronics has addressed this issue by coming up with a low-loss passive technology called IPD™ (Integrated Passive Devices) RLC06 technology, which is a passive process on glass substrate featuring high RF performance and high level of integration with either wire bonded or flip chipped interconnects. In this paper, a 2.8mm×2.8mm WLCSP (Wafer Level Chip Scale Package) was used as test vehicle. The drop impact performance of the test vehicle employing two different RDL (ReDistribution Layer) process technologies was evaluated through finite element modeling. Maximum peeling stress in the regions of interest was extracted and analyzed for comparison. Actual drop test was performed to characterize the drop impact durability of the WLCSP. It is found that the simulation result agrees very well with the experimental observations in terms of failure location and relative drop test robustness of the two structures. However, the small difference in maximum peeling stress may not be able to justify their big difference in drop test reliability. It could be due to the intrinsic limitation of the numerical method adopted as well as to the different failure locations of the two structures, where there may be different material toughness. The validated model was then extended to optimize the design of Al pad and Cu via of the alternative bump pad for the WLSCP package subjected to drop test.