Thermal behavior of stack-based 3D ICs

• Main Authors: Souare, Papa Momar, de Crecy, Francois, Fiori, Vincent, Ben Jamaa, Haykel, Farcy, Alexis, Gallois-Garreignot, Sebastien, Borbely, Andras, Lhostis, Sandrine, Leduc, Patrick, Cheramy, Severine, Tavernier, Clement, Michailos, Jean
• Format: Conference Proceeding
• Language: English
• DOI: 10.1109/ESTC.2012.6542107

The 3D IC technology has attracted much interest in the recent past as a mean to efficiently improve performance and miniaturization of electronic integrated circuits (IC) [1]. The integration is based on three dimensional (3D) die stacking, connected thanks to Through Silicon Vias (TSV), μcopper pillars and large copper pillars. Although this approach offers several advantages in terms of electric features, the thermal management is widely identified as one of the key challenges [2]. The purpose of this study is to present a numerical model based on finite elements, to be calibrated and validated by experimental means (i.e. electrical in-situ and thermal IR measurements). In this paper, a presentation of our test chip (stacking, heaters and embedded sensors), the impact of various geometric parameters, the behavior of TSV around heated areas, and thermal properties of materials in the 3D stack-based will be presented. Our numerical model is composed of two chips stacked on a BGA. We use homogenized properties of TSV, Cu-Pillars (CP), μCP and BEOL. The best combination of geometrical (diameter, pitch) and technological (SiO2 and Silicium thickness, underfill properties) parameters in terms of thermal dissipation is extracted through design of experiments. We aim to know the internal thermal behavior despite the strong influence of poorly known boundary conditions. Finally, by proposing a whole numerical and experimental approach, this paper brings insights for early phase development of 3D ICs on self heating questions.