Analyzing the Efficiency of L1 Caches for Reliable Hybrid-Voltage Operation Using EDC Codes

The increasing demand for highly miniaturized battery-powered ultralow cost systems (e.g., below 1 dollar) in emerging applications such as body, urban life and environment monitoring, and so on, has introduced many challenges in chip design. Such applications require high performance occasionally a...

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Bibliographic Details
Published in:IEEE transactions on very large scale integration (VLSI) systems 2014-10, Vol.22 (10), p.2211-2215
Main Authors: Maric, Bojan, Abella, Jaume, Valero, Mateo
Format: Article
Language:English
Subjects:
Battery
Benchmark testing
Caches
Computer architecture
Design engineering
Efficiency
Electric potential
embedded real-time
Energy consumption
Energy management
Gain
low energy
performance guarantees
Reliability
SRAM cells
Transistors
Very large scale integration
Voltage
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Summary:The increasing demand for highly miniaturized battery-powered ultralow cost systems (e.g., below 1 dollar) in emerging applications such as body, urban life and environment monitoring, and so on, has introduced many challenges in chip design. Such applications require high performance occasionally and very little energy consumption during most of the time to extend battery lifetime. In addition, they require real-time guarantees. Caches have been shown to be the most critical blocks in these systems due to their high energy/area consumption and hard-to-predict behavior. New, simple, hybrid-voltage operation (high V cc and ultralow V cc ), single-V cc domain L1 cache architectures based on replacing energy-hungry bitcells (e.g., 10T) by more energy-efficient and smaller cells (e.g., 8T) enhanced with error detection and correction codes have been recently proposed. Such designs provide significant energy and area efficiency without jeopardizing reliability levels to still provide strong performance guarantees. In this brief, we analyze the efficiency of these designs during ultralow voltage operation. We identify the limits of such approaches by finding an energy-optimal voltage region through experimental models. The experimental results show that area efficiency is always achieved in the range 200-400 mV, whereas both energy and area gains occur above 250 mV, i.e., in near-threshold regime.
ISSN:1063-8210
1557-9999
DOI:10.1109/TVLSI.2013.2282498