Instruction set extensions of AES algorithms for 32-bit processors

• Main Authors: Ben Hadjy Youssef, Noura, El Hadj Youssef, Wajih, Machhout, Mohsen, Tourki, Rached, Torki, Kholdoun
• Format: Conference Proceeding
• Language: English
• Subjects: AES; decryption; Embedded processor; Encryption; Field programmable gate arrays; FPGA and ASIC implementation; Hardware; LEON2; Program processors; Registers
• ISSN: 1071-6572; 2153-0742
• DOI: 10.1109/CCST.2014.6986988

Embedded processors are an integral part of many communications devices such as mobile phones, secure access to private networks, electronic commerce and smart cards. However, such devices often provide critical functions that could be sabotaged by malicious entities. The supply of security for data exchange on basis of embedded systems is a very important objection to accomplish. This paper focuses on instruction set extensions of symmetric key algorithm. The main contribution of this work is the extension of SPARC V8 LEON2 processor core with cryptographic Instruction Set Extensions. The proposed cryptographic algorithm is Advanced Encryption Standard (AES). Our customized instructions offer a cryptographic solution for embedded devices, in order to ensure communications security. Furthermore, as embedded systems are extremely resource constrained devices in terms of computing capabilities, power and memory area; these technological challenges are respected. Our extended LEON2 SPARC V8 core with cryptographic ISE is implemented using Xilinx XC5VFX70t FPGA device and an ASIC CMOS 40 nm technology. The total area of the resulting Chip is about 0.28 mm 2 and can achieve an operating frequency of 3.33 GHz. The estimated power consumption of the chip was 13.3 mW at 10 MHz. Hardware cost and power consumption evaluation are provided for different clock frequencies, the achieved results show that our circuit is able to be arranged in many security domains such as embedded services routers, real-time multimedia applications and smartcard.