A low-resource 32-bit datapath ECDSA design for embedded applications

• Main Authors: Ben Hadjy Youssef, Noura, El Hadj Youssef, Wajih, Machhout, Mohsen, Tourki, Rached, Torki, Kholdoun
• Format: Conference Proceeding
• Language: English
• Subjects: Algorithm design and analysis; Application specific integrated circuits; Digital signatures; ECDSA; Elliptic Curve Cryptography; Elliptic curves; Field programmable gate arrays; Finite field arithmetic; FPGA/ASIC Implementation; Galois fields; Hardware
• ISSN: 1071-6572; 2153-0742
• DOI: 10.1109/CCST.2014.6987045

In this paper we describe a hardware implementation of a low resource digital signature design using Elliptic Curve Digital Signature Algorithm (ECDSA). The implementation of ECDSA is based on the recommended GF (2 163 ) NIST Elliptic Curve Cryptography (ECC). Elliptic curve based systems can be implemented with much smaller parameters, leading to significant performance advantages. Such performance improvements are particularly important for embedded applications where computing power, memory, and battery life of devices are more constrained. In order to meet these fierce constraints, our design has a 32bit word size. The design flow starts from an architectural description at the RTL level in order to interact easily with current commercial hardware synthesis tools. After simulation and synthesis steps, implementation is achieved on a Virtex-5 XC5FX70t FPGA using Xilinx's ISE design suite. Furthermore, the design was also implemented in both 65 nm and 40 nm CMOS ASIC design for performance comparisons. The Virtex-5 design requires 10838 slices with 1.58 ms (207.097 MHz) for signature generation and 12922 slices with 1.953 ms (195.309 MHz) for verification process. The ASIC design has an area of 467617 μm 2 (726798 μm 2 ) for signature generation and 260713μm 2 (408350 μm 2 ) for signature verification respectively using CMOS 65 nm and 40 nm technology. When running at a frequency of 500 MHz, the design consumes 2.71 mW (1.56 mW) of power for generation process and 3.90 mW (2.23 mW) for verification using a CMOS 65 nm and 40 nm technology respectively. From the implementation results, it is verified that the proposed ECDSA design are faster compared to literature with less power dissipation.