4.5 The Xeon® processor E5-2600 v3: A 22nm 18-core product family

• Main Authors: Bowhill, Bill, Stackhouse, Blaine, Nassif, Nevine, Zibing Yang, Raghavan, Arvind, Morganti, Charles, Houghton, Chris, Krueger, Dan, Franza, Olivier, Desai, Jayen, Crop, Jason, Bradley, Dave, Bostak, Chris, Bhimji, Sal, Becker, Matt
• Format: Conference Proceeding
• Language: English
• Subjects: Clocks; Inductors; Optimization; Program processors; Regulators; Synchronization; Voltage control
• ISSN: 0193-6530; 2376-8606
• DOI: 10.1109/ISSCC.2015.7062934

The next-generation enterprise Xeon server processor maximum configuration supports 18 dual-threaded 64b Haswell cores, 45MB L3 cache, 4 DDR4-2133MHz memory channels, 40 8GT/s PCIe lanes, and 60 9.6GT/S QPI lanes. The processor has 5.56B transistors on a 31.9mm×20.8mm die in Intel's high-K metal-gate tri-gate 22nm CMOS technology with 11 metal layers and achieves a 33% performance boost, on average, over previous generations. Two additional metal layers enable area optimization and performance improvement. The design supports a wide range of configurations, including thermal design power ranging from 55 to 165W and frequencies ranging from 1.6 to 3.8GHz. Key architectural innovations include the addition of AVX2 technology, DDR4, and fully integrated voltage regulators (FIVR) that enable per-core p-states and uncore frequency scaling. Motherboard power delivery for high-performance microprocessors has become a significant design challenge that threatens the ability to cost effectively deliver high dynamic power at low voltage. To address this challenge, a fully integrated voltage regulator solution (FIVR) has been implemented, which enables several power-performance and platform optimizations. With FIVR, power is delivered to the die from a single mother-board voltage regulator (MBVR) at an elevated voltage of 1.8V, which results in a square-law reduction in power losses in the platform. FIVRs have a wide input voltage range of ±~200mV which simplifies the design of the platform delivery network and enables higher MBVR efficiencies. FIVR delivers cost reductions by reducing the number of MBVRs and the total number of VR phases required. The socket and package also require fewer power pins. The result is that total platform power is lower in the FIVR design, when compared to a classic MBVR solution at iso performance and cost.