Coherence protocol for transparent management of scratchpad memories in shared memory manycore architectures

• Main Authors: Alvarez, Lluc, Vilanova, Lluís, Moreto, Miquel, Casas, Marc, Gonzàlez, Marc, Martorell, Xavier, Navarro, Nacho, Ayguadé, Eduard, Valero, Mateo
• Format: Conference Proceeding
• Language: English
• Subjects: Arquitectura de computadors; Cache memory; Compiladors (Programes d'ordinador); Compilers (Computer programs); Gestió de memòria (Informàtica); Hardware > Hardware validation; Hardware > Integrated circuits > Semiconductor memory; Informàtica; Instruction sets; Memory management (Computer science); Memòria ràpida de treball (Informàtica); Àrees temàtiques de la UPC
• ISSN: 1063-6897; 2575-713X
• DOI: 10.1145/2749469.2750411

The increasing number of cores in manycore architectures causes important power and scalability problems in the memory subsystem. One solution is to introduce scratchpad memories alongside the cache hierarchy, forming a hybrid memory system. Scratchpad memories are more power-efficient than caches and they do not generate coherence traffic, but they suffer from poor programmability. A good way to hide the programmability difficulties to the programmer is to give the compiler the responsibility of generating code to manage the scratchpad memories. Unfortunately, compilers do not succeed in generating this code in the presence of random memory accesses with unknown aliasing hazards. This paper proposes a coherence protocol for the hybrid memory system that allows the compiler to always generate code to manage the scratchpad memories. In coordination with the compiler, memory accesses that may access stale copies of data are identified and diverted to the valid copy of the data. The proposal allows the architecture to be exposed to the programmer as a shared memory manycore, maintaining the programming simplicity of shared memory models and preserving backwards compatibility. In a 64-core manycore, the coherence protocol adds overheads of 4% in performance, 8% in network traffic and 9% in energy consumption to enable the usage of the hybrid memory system that, compared to a cache-based system, achieves a speedup of 1.14x and reduces on-chip network traffic and energy consumption by 29% and 17%, respectively.