Loading…
A Resilient Framework for Fault-Tolerant Operation of Modular Multilevel Converters
This paper presents a resilient framework for fault-tolerant operation in modular multilevel converters (MMCs) to facilitate normal operation under internal and external fault conditions. This framework is realized by designing and implementing a supervisory algorithm and a postfault restoration sch...
Saved in:
Published in: | IEEE transactions on industrial electronics (1982) 2016-05, Vol.63 (5), p.2669-2678 |
---|---|
Main Authors: | , |
Format: | Article |
Language: | English |
Subjects: | |
Citations: | Items that this one cites Items that cite this one |
Online Access: | Get full text |
Tags: |
Add Tag
No Tags, Be the first to tag this record!
|
Summary: | This paper presents a resilient framework for fault-tolerant operation in modular multilevel converters (MMCs) to facilitate normal operation under internal and external fault conditions. This framework is realized by designing and implementing a supervisory algorithm and a postfault restoration scheme. The supervisory algorithm includes monitoring and decision-making units to detect and identify faults by analyzing the circulating current and submodule capacitor voltages in a very short time. The postfault restoration scheme is proposed to immediately replace the faulty submodule with the redundant healthy one. The restoration is achieved by virtue of a multilevel modular capacitor-clamped dc/dc converter (MMCCC), which is redundantly aggregated to each arm of the MMC. This design effectively guarantees smooth mode transition and handles the failure of multiple submodules in a short time interval. In addition, a modified modulation scheme is presented to ensure submodule capacitor voltage balancing of the MMC without implementing any additional hardware. Fast fault identification, a fully modular structure, and robust postfault restoration are the main features of the proposed framework. Digital time-domain simulation studies are conducted on a 21-level MMC to confirm the effectiveness and resilience of the proposed fault-tolerant framework during internal and external faults. Furthermore, the proposed framework is implemented in the FPGA-based RT-LAB real-time simulator platform to validate its resilience in a hardware-in-the-loop setup. |
---|---|
ISSN: | 0278-0046 1557-9948 |
DOI: | 10.1109/TIE.2016.2516968 |