Minerva: Enabling Low-Power, Highly-Accurate Deep Neural Network Accelerators

• Main Authors: Reagen, Brandon, Whatmough, Paul, Adolf, Robert, Rama, Saketh, Lee, Hyunkwang, Lee, Sae Kyu, Hernandez-Lobato, Jose Miguel, Wei, Gu-Yeon, Brooks, David
• Format: Conference Proceeding
• Language: English
• Subjects: Circuit faults; Hardware; Integrated circuit modeling; Libraries; Optimization; Random access memory; Space exploration
• ISSN: 1063-6897; 2575-713X
• DOI: 10.1109/ISCA.2016.32

The continued success of Deep Neural Networks (DNNs) in classification tasks has sparked a trend of accelerating their execution with specialized hardware. While published designs easily give an order of magnitude improvement over general-purpose hardware, few look beyond an initial implementation. This paper presents Minerva, a highly automated co-design approach across the algorithm, architecture, and circuit levels to optimize DNN hardware accelerators. Compared to an established fixed-point accelerator baseline, we show that fine-grained, heterogeneous datatype optimization reduces power by 1.5×; aggressive, inline predication and pruning of small activity values further reduces power by 2.0×; and active hardware fault detection coupled with domain-aware error mitigation eliminates an additional 2.7× through lowering SRAM voltages. Across five datasets, these optimizations provide a collective average of 8.1× power reduction over an accelerator baseline without compromising DNN model accuracy. Minerva enables highly accurate, ultra-low power DNN accelerators (in the range of tens of milliwatts), making it feasible to deploy DNNs in power-constrained IoT and mobile devices.