A fast, asP, RGD arbiter

This paper presents the design of a high-throughput, low-latency, asP*, RGD arbiter. Spice simulations for an implementation in a 0.8 /spl mu/ CMOS process show a request-to-grant delay of 0.74 ns and a done-to-grant-delay of 0.42 ns. Maximum throughput of requests from a single client is one grant...

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Bibliographic Details
Main Authors: Greenstreet, M.R., Ono-Tesfaye, T.
Format: Conference Proceeding
Language:English
Subjects:
Application specific processors
Circuits
Clocks
CMOS process
Delay
Design optimization
Logic design
Metastasis
Synchronization
Throughput
Online Access:Request full text
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Summary:This paper presents the design of a high-throughput, low-latency, asP*, RGD arbiter. Spice simulations for an implementation in a 0.8 /spl mu/ CMOS process show a request-to-grant delay of 0.74 ns and a done-to-grant-delay of 0.42 ns. Maximum throughput of requests from a single client is one grant per 1.8 ns; if both clients make request aggressively, the arbiter can produce one grant per 1.2 ns. In addition to presenting a high-performance design, this paper examines trade-offs in performance driven design. In particular, logic delay seems to dominate metastability concerns when optimizing performance.
ISSN:1522-8681
DOI:10.1109/ASYNC.1999.761532