Design-Oriented Analysis for Miller Compensation and Its Application to Multistage Amplifier Design

• Published in: IEEE journal of solid-state circuits 2017-02, Vol.52 (2), p.517-527
• Main Authors: Wanyuan Qu, Singh, Shashank, Yongjin Lee, Young-Suk Son, Gyu-Hyeong Cho
• Format: Article
• Language: English
• Subjects: Amplifier; Bandwidth; Capacitance; CMOS process; Feedforward neural networks; frequency compensation; large-capacitive load (<italic xmlns:ali="http://www.niso.org/schemas/ali/1.0/" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">CL ); Miller compensation; multistage amplifier; Poles and zeros; Power demand
• ISSN: 0018-9200; 1558-173X
• DOI: 10.1109/JSSC.2016.2619677

A design-oriented analysis (DOA) method is presented, which lends sufficient insights into various Miller compensation schemes. The method predicts the nondominant poles of the Miller-compensated amplifiers in an intuitive manner, and it serves as a good supplement to the conventional analysis. The usage of DOA is verified by the various design examples given in this paper. Guided by DOA, a multistage amplifier capable of driving a large-capacitive load (C_{L} ) with low power consumption is presented. This amplifier employs an active zero to extend its Miller loop bandwidth, thereby pushing the amplifier's nondominant poles to high frequencies and achieving larger gain bandwidth (GBW). Fabricated in a 0.18-\mu \text{m} CMOS process, the amplifier achieves 1.18-MHz GBW and 59.6° phase margin when driving an 18-nF C_{L} , while consuming 69.6 \mu \text{W} from a 1.2-V supply. The design shows improved figures-of-merit compared with the prior state-of-the-art Miller-compensated multistage amplifiers.