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3.7 A 1920×1080 30fps 2.3TOPS/W stereo-depth processor for robust autonomous navigation
This paper presents a stereo vision processor that fully implements the SGM algorithm on a single chip. The design uses a new image-scanning stride to enable a deeply pipelined implementation with ultra-wide (1612b) custom SRAM for 1.64Tb/s on-chip access bandwidth. Our design is the first ASIC to r...
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| creator | Ziyun Li Qing Dong Saligane, Mehdi Kempke, Benjamin Shijia Yang Zhengya Zhang Dreslinski, Ronald Sylvester, Dennis Blaauw, David Hun Seok Kim |
| description | This paper presents a stereo vision processor that fully implements the SGM algorithm on a single chip. The design uses a new image-scanning stride to enable a deeply pipelined implementation with ultra-wide (1612b) custom SRAM for 1.64Tb/s on-chip access bandwidth. Our design is the first ASIC to report performance under the industrial standard KITTI benchmark that renders realistic automobile scenes. The proposed design supports 512-level depth resolution on full HD (1920×1080) resolution with real-time 30fps, consuming 836mW from a 0.75V supply in 40nm CMOS. We also integrate the stereo chip with a quadcopter and demonstrate its operation in real-time flight. |
| doi_str_mv | 10.1109/ISSCC.2017.7870261 |
| format | conference_proceeding |
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| fulltext | fulltext_linktorsrc |
| identifier | EISSN: 2376-8606 |
| ispartof | 2017 IEEE International Solid-State Circuits Conference (ISSCC), 2017, p.62-63 |
| issn | 2376-8606 |
| language | eng |
| recordid | cdi_ieee_primary_7870261 |
| source | IEEE Xplore All Conference Series |
| subjects | Bandwidth High definition video Image resolution Memory management Program processors Random access memory Real-time systems |
| title | 3.7 A 1920×1080 30fps 2.3TOPS/W stereo-depth processor for robust autonomous navigation |
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