A 14-nm 0.14-psrms Fractional-N Digital PLL With a 0.2-ps Resolution ADC-Assisted Coarse/Fine-Conversion Chopping TDC and TDC Nonlinearity Calibration

A digital fractional-N phase-locked loop (PLL) is presented. It achieves 137and 142-fs rms jitter integrating from 10 kHz to 10 MHz and from 1 kHz to 10 MHz, respectively. With a frequency multiplication ratio of 207.0019231 [digitally controlled oscillator (DCO) frequency is 50 kHz away from an int...

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Bibliographic Details
Published in:IEEE journal of solid-state circuits 2017-12, Vol.52 (12), p.3446-3457
Main Authors: Chih-Wei Yao, Ronghua Ni, Chung Lau, Wanghua Wu, Godbole, Kunal, Yongrong Zuo, Sangsoo Ko, Nam-Seog Kim, Sangwook Han, Ikkyun Jo, Joonhee Lee, Juyoung Han, Daehyeon Kwon, Chulho Kim, Shinwoong Kim, Sang Won Son, Cho, Thomas Byunghak
Format: Article
Language:English
Subjects:
all-digital phase-locked loop (ADPLL)
Analog to digital conversion
Analog to digital converters
Calibration
CMOS
Computer architecture
Converters
Cutting
Delays
digital phase-locked loop (PLL)
digitally controlled oscillator (DCO)
Field effect transistors
fractional spur
fractional-N PLL
frequency synthesizer
Jitter
Microprocessors
MIMO
Nonlinearity
Oscillators
Phase locked loops
Phase noise
time-to-digital converter (TDC)
Vibration
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Description
Summary:A digital fractional-N phase-locked loop (PLL) is presented. It achieves 137and 142-fs rms jitter integrating from 10 kHz to 10 MHz and from 1 kHz to 10 MHz, respectively. With a frequency multiplication ratio of 207.0019231 [digitally controlled oscillator (DCO) frequency is 50 kHz away from an integer multiple of the 26-MHz reference clock], a -78.6-dBc fractional spur is achieved for an output clock that runs at half of the DCO frequency. Time-to-digital converter (TDC) chopping technique, TDC fine conversion through successive approximation register analog-to-digital converters (SARADCs), and TDC nonlinearity calibration improve integrated phase noise and fractional spurs. This design meets the performance requirement of the 256-QAM 4 × 4 MIMO LTE standard in 5-GHz ISM band and also the 5G cellular 64-QAM standard in 28-GHz band. This work, implemented in a 14-nm fin-shaped field effect transistor (FinFET) CMOS process, is integrated to a cellular RF integrated circuit supporting advanced carrier aggregation operation. This PLL draws 13.4 mW and occupies 0.257 mm 2 .
ISSN:0018-9200
1558-173X
DOI:10.1109/JSSC.2017.2742518