Generational changes of flip chip interconnection technology

• Main Authors: Wen Shan Tsai, Huang, C. Y., Chung, C. Key, Yu, K. H., Lin, C. F.
• Format: Conference Proceeding
• Language: English
• Subjects: Bonding; Compounds; Copper; Flip-chip devices; Plating; Silicon; Substrates
• ISSN: 2150-5942
• DOI: 10.1109/IMPACT.2017.8255955

Flip chip (FC) assembly technology was developed by IBM in 1960s and widely used in high functional performances of electronic devices in computer, military, mobile, automobile etc. The use of solder bumps to make electrical connection between the substrate and chip can provide shorter path and reduce latency issues as compared to wire bonding. Additionally, flip chip is an area array bonding, which allows high I/O (Input/Output) density within a single die, and thus driving the semiconductor scaling process. Over the decades, the number of interconnection within flip chip devices has been increased from hundreds to half million bump joints. For the purpose to achieving the massive high I/O counts, the miniature of bump size and bump pitch plays a significant role, and also face technology challenges. Chip interconnection bumps technology has been evolved over fifty years. Generally, it could be divided into three generations in according to the connection method. The first generation typically has the bump pitch over 130μm, while the second generation's bump pitch is within a range from 40 to 130 μm. And the most recent one (the third generation) has been developed to be smaller than 30μm. Each generation has unique bonding technology and encapsulation materials to make different assembly packages and form factors. For the bump pitch over 130μm, which is normally composed of solder ball, is so called controller collapse chip connect (C4) bumps. The bumps in the device, up to nearly thousand counts, are usually bonded on to ceramic or organic substrate using flip chip bonder with fluxing and reflow soldering processes. Further, flux cleaning is introduced to remove flux residue, which is followed by the underfill or mold encapsulation process to protect the solder connections. Flip Chip Ball Grid Array (FCBGA) and Flip Chip Chip Scale Package (FCCSP) are the classic two package types of this C4 joint generation. As for the interconnection technology with bump pitch between 40 to 130μm, which is so-called micro bump or chip connection (C2) bumps, the thermal-mechanical warpage and bonding precision are the major challenges. The copper pillar with thinner solder tip is generally produced to meet the finer pitch requirements. However, the collapsing process during soldering is hard to compensate the warpage induced by CTE-mismatch between chips and substrates, which drives the implementation of through silicon interposer (TSI) to be a solution for the thermal