A 5GHz 370fsrms 6.5mW clock multiplier using a crystal-oscillator frequency quadrupler in 65nm CMOS

Phase noise performance of ring-oscillator-based (RO-based) clock multipliers is typically limited by oscillator noise. The most power-efficient method for improving the phase noise of such clock multipliers is by increasing the oscillator noise suppression bandwidth (F BW ). While F BW depends on t...

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Bibliographic Details
Main Authors: Megawer, Karim M., Elkholy, Ahmed, Coombs, Daniel, Ahmed, Mostafa G., Elmallah, Ahmed, Hanumolu, Pavan Kumar
Format: Conference Proceeding
Language:eng ; jpn
Subjects:
Calibration
Clocks
Delays
Jitter
Noise measurement
Phase locked loops
Phase noise
Online Access:Request full text
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Summary:Phase noise performance of ring-oscillator-based (RO-based) clock multipliers is typically limited by oscillator noise. The most power-efficient method for improving the phase noise of such clock multipliers is by increasing the oscillator noise suppression bandwidth (F BW ). While F BW depends on the type of clock multiplier, the maximum achievable F BW is limited by the reference frequency (F ref ). For instance, in phase-locked loops (PLLs) F BW = F ref /10, while multiplying delay-locked loops (MDLLs) [1] and injection-locked clock multipliers (ILCMs) [2] can achieve F BW of F ref /4 and F ref /6, respectively. Exploiting this behavior, the MDLL in [1] and the ILCM in [2] achieved excellent performance at the expense of using a high-frequency low-noise reference (REF) clock and a small multiplication factor (N
ISSN:2376-8606
DOI:10.1109/ISSCC.2018.8310349