FPGA-based implementation of TZsearch algorithm for H.265/HEVC standard

There are several standard techniques that have emerged within the framework of international video coding standards. The newest and most efficient is the H.265 / HEVC. However, its techniques possess a degree of complexity which remains increasingly high and generate consequently a long computation...

Full description

Saved in:
Bibliographic Details
Main Authors: Haddar, Rahma, Chaari, Asma, Kibeya, Hassan, Ben Ayed, Mohamed Ali, Masmoudi, Nouri
Format: Conference Proceeding
Language:English
Subjects:
Computer architecture
Diamond
Encoding
FPGA
H.265/HEVC
Hardware
Motion estimation
Random access memory
TZS
VHDL
Online Access:Request full text
Tags: Add Tag
No Tags, Be the first to tag this record!
Description
Summary:There are several standard techniques that have emerged within the framework of international video coding standards. The newest and most efficient is the H.265 / HEVC. However, its techniques possess a degree of complexity which remains increasingly high and generate consequently a long computation time, in particular the technique of motion estimation. This operation is largely involved in compression by eliminating temporal redundancies and it is the most sensitive part in a video encoder. As a result, algorithmic optimizations are required to reduce the complexity and computational time. We are interested in the most efficient algorithm for motion estimation which is the "TZ search". In fact, this work aims to implement an optimized fast search algorithm that maintains the good performance of the process. So, it proposes hardware architecture of fast motion estimation algorithm for H.265/HEVC standard using Test Zone Search (TZS). It presents pipeline processing techniques, minimum latency and maximum bite rate. The proposed VHDL code has been tested through Xilinx Virtex-7 FPGA circuit. The frequency result is estimated at 197 Mhz.
ISSN:2573-539X
DOI:10.1109/STA.2017.8314939