TileNET: Scalable Architecture for High-Throughput Ternary Convolution Neural Networks Using FPGAs

• Main Authors: Vikram, Sahu Sai, Pant, Vibha, Mody, Mihir, Purnaprajna, Madhura
• Format: Conference Proceeding
• Language: English
• Subjects: Acceleration; Computer architecture; Convolution; Electronic mail; Field programmable gate arrays; Neural networks; Throughput
• ISSN: 2380-6923
• DOI: 10.1109/VLSID.2018.113

Convolution Neural Networks (CNNs) are becoming increasing popular in Advanced driver assistance systems (ADAS) and Autonomated driving (AD) for camera perception enabling multiple applications like object detection, lane detection and semantic segmentation. Ever increasing need for high resolution multiple cameras around car necessitates a huge-throughput in the order of about few 10's of TeraMACs per second (TMACS) along with high accuracy of detection. Existing implementations do not scale, with performance ranging only in the order of a few Giga operations per second. This paper, proposes a novel tiled architecture for CNNs that uses only ternarized weights, while input and output features are kept full precision resulting in minimal loss of accuracy. The proposed solution is implemented on Virtex-7 FPGA resulting in throughput of 13.76 TOPS. The post-implementation power simulation for AlexNet consumes 16 W, orders of magnitude lower than exist in GPUs.