Modeling of NBTI Kinetics in RMG Si and SiGe FinFETs, Part-I: DC Stress and Recovery

• Published in: IEEE transactions on electron devices 2018-05, Vol.65 (5), p.1699-1706
• Main Authors: Parihar, Narendra, Southwick, Richard G., Wang, Miaomiao, Stathis, James H., Mahapatra, Souvik
• Format: Article
• Language: English
• Subjects: Bulk trap generation; FinFET; hole trapping; interface trap generation; Kinetic theory; Logic gates; Mathematical model; Negative bias temperature instability; negative bias temperature instability (NBTI); replacement metal gate (RMG) high-K metal gate (HKMG); SiGe channel; Silicon germanium; Stress; Thermal variables control; ultrafast characterization; voltage acceleration factor (VAF)
• ISSN: 0018-9383; 1557-9646
• DOI: 10.1109/TED.2018.2819023

An ultrafast (10- \mu \text{s} delay) measurement technique is used to characterize the negative bias temperature instability-induced threshold voltage shift ( \Delta {V}_{T} ) in replacement metal gate-based high-K metal gate Si and SiGe p-FinFETs. The dc stress-recovery \Delta {V}_{T} time kinetics, voltage acceleration factor (VAF), and temperature activation energy ( {E}_{A} ) are compared for different germanium percentages (Ge%) in the channel and nitrogen percentages (N%) in the gate-stack. A comprehensive physical model framework based on uncorrelated contributions from the generation of interface ( \Delta {V}_{\mathrm {IT}} ) and bulk oxide ( \Delta {V}_{\mathrm {OT}} ) traps and hole trapping in preexisting defects ( \Delta {V}_{\mathrm {HT}} ) is used to explain the measured data. The impact of Ge% and N% on \Delta {V}_{T} , VAF, {E}_{A} , temperature (T) dependence of VAF, and stress bias ( {V}_{\mathrm {GSTR}} ) dependence of {E}_{A} are quantified. The interface trap generation component is independently verified by direct-current {I} - {V} (DCIV) measurements.