Execution trace graph based interface synthesis of signal processing dataflow programs for heterogeneous MPSoCs

• Main Authors: Bezati, E., Brunet, S. Casale, Mattavelli, M.
• Format: Conference Proceeding
• Language: English
• Subjects: C++ languages; Clocks; Computer architecture; Hardware; Performance analysis; Random access memory; Software
• ISSN: 2576-2303
• DOI: 10.1109/ACSSC.2017.8335388

Heterogeneous multiprocessor system-on-chip MPSoCs platforms can provide effective implementation solutions for a wide range of applications. Such processing platform potentially provides low-power massive parallelism capabilities, but the real challenge is the difficulty of programming applications so as to fully exploit their capabilities. Dataflow programming approaches, including the ones based on the CAL dataflow programming language, provides a solution for effectively designing both the reconfigurable hardware processing components such as FPGAs and the sequential multi-core CPU components. One of the more challenging design task for heterogeneous platforms is the configuration of the interface between each processing or storage component. It consists of determining the number and type of interfaces for the communication between the reconfigurable hardware and the sequential processor arrays of the MPSoCs. In this paper, a methodology that systematically identify and synthesizes the necessary interfaces when a dataflow program is first partitioned and mapped on the processing component of a MPSoCs. The methodology is based on the analysis of the data exchanges extracted by the abstract Execution Trace Graph of the dataflow program.