Power optimization through peripheral circuit reusing integrated with loop tiling for RRAM crossbar-based CNN

• Main Authors: Ni, Yuanhui, Chen, Weiwen, Cui, Wenjuan, Zhou, Yuanchun, Qiu, Keni
• Format: Conference Proceeding
• Language: English
• Subjects: Data transfer; Embedded systems; Energy consumption; Field programmable gate arrays; Kernel; Power demand; Schedules
• ISSN: 1558-1101
• DOI: 10.23919/DATE.2018.8342193

Convolutional neural networks (CNNs) have been proposed to be widely adopted to make predictions on a large amount of data in modern embedded systems. Prior studies have shown that convolutional computations which consist of numbers of multiply and accumulate (MAC) operations, serve as the most computationally expensive portion in CNN. Compared to the manner of executing MAC operations in GPU and FPGA, CNN implementation in the RRAM crossbar-based computing system (RCS) demonstrates the outstanding advantages of high performance and low power. However, the current design is energy-unbalanced among the three parts of RRAM crossbar computation, peripheral circuits and memory accesses, the latter two factors can significantly limit the potential gains of RCS. Addressing the problem of high power overhead of peripheral circuits in RCS, the Peripheral Circuit Unit (PeriCU)-Reuse scheme has been proposed to meet given power budget. In this paper, it is further observed that memory accesses can be bypassed if two adjacent layers are assigned in different PeriCUs. In this way, memory accesses can be reduced and thus the performance and power can be improved. A loop tiling technique is proposed to save memory accesses. The experiments of two convolutional applications validate that the proposed loop tiling technique can reduce energy consumption by 61.7%.