Finite State Machine Based Countermeasure for Cryptographic Algorithms

In this work, we present a novel FPGA-based implementation of the AES algorithm which has a two-layered resistance against power analysis attacks. Our countermeasure is based on the concept of finite state machine equipped with a random number generator. Beyond masking the intermediate variables as...

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Bibliographic Details
Main Authors: Attari, Sadegh, Shahmirzadi, Aein Rezaei, Salmasizadeh, Mahmoud, Gholampour, Iman
Format: Conference Proceeding
Language:English
Subjects:
Clocks
Correlation
Field programmable gate arrays
Finite state machine
Hiding
Masking
Power demand
Side-channel attacks
Side-channel-attack
Online Access:Request full text
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Summary:In this work, we present a novel FPGA-based implementation of the AES algorithm which has a two-layered resistance against power analysis attacks. Our countermeasure is based on the concept of finite state machine equipped with a random number generator. Beyond masking the intermediate variables as the first layer of defense, we randomize the sequences of operations and add dummy computations as the second layer of defense. Therefore, the first order attack is prevented and the number of power traces needed for a successful second order attack is vastly increased and the correlation coefficient is decreased, as expected.
ISSN:2475-2371
DOI:10.1109/ISCISC.2017.8488336