Dynamic Partial Reconfiguration of Customized Single-Row Accelerators

• Published in: IEEE transactions on very large scale integration (VLSI) systems 2019-01, Vol.27 (1), p.116-125
• Main Authors: Paulino, Nuno M. C., Ferreira, Joao Canas, Cardoso, Joao M. P.
• Format: Article
• Language: English
• Subjects: Acceleration; Accelerators; Binary acceleration; coprocessor; dynamic partial reconfiguration (DPR); Embedded systems; Field programmable gate arrays; field-programmable gate array (FPGA); Hardware; Kernel; Kernels; loop accelerator; modulo scheduling; Program processors; Reconfiguration; Runtime; very long instruction word (VLIW); VLIW
• ISSN: 1063-8210; 1557-9999
• DOI: 10.1109/TVLSI.2018.2874079

The use of specialized accelerator circuits is a feasible solution to address performance and energy issues in embedded systems. This paper extends a previous field-programmable gate array-based approach that automatically generates pipelined customized loop accelerators (CLAs) from runtime instruction traces. Despite efficient acceleration, the approach suffered from high area and resource requirements when offloading a large number of kernels from the target application. This paper addresses this by enhancing the CLA with dynamic partial reconfiguration (DPR) support. Each kernel to accelerate is implemented as a variant of a reconfigurable area of the CLA which hosts all functional units and configuration memory. Evaluation of the proposed system is performed on a Virtex-7 device. We show, for a set of 21 kernels, that when comparing two CLAs capable of accelerating the same subset of kernels, the one which benefits from DPR can be up to 4.3\times smaller. Resorting to DPR allows for the implementation of CLAs which support numerous kernels without a significant decrease in operating frequency and does not affect the initiation intervals at which kernels are scheduled. Finally, the area required by a CLA instance can be further reduced by increasing the IIs of the scheduled kernels.