A High-Performance VLSI Architecture of the Present Cipher and its Implementations for SoCs

• Main Authors: Pandey, Jai Gopal, Goel, Tarun, Nayak, Mausam, Mitharwal, Chhavi, Karmakar, Abhijit, Singh, Raj
• Format: Conference Proceeding
• Language: English
• Subjects: ASIC; Ciphers; Clocks; Computer architecture; Encryption; Field programmable gate arrays; IP networks; Lightweight cryptography; PRESENT block cipher; SoCs; VLSI architectures
• ISSN: 2164-1706
• DOI: 10.1109/SOCC.2018.8618487

The essence of internet-of-things (IoT) and cyber-physical systems (CPS) infrastructures is primarily based on privacy and security of communicated data. In these resource-constrained applications, lightweight cryptography plays a vital role for data security. In this paper, we propose a highperformance and power-efficient VLSI architecture for the PRESENT block cipher and its integration in a system-on-chip (SoC) environment. The architecture is based on 8-bit datapath and requires 48 clock cycles for processing of 64-bit plaintext and 128-bit key. When implemented on Xilinx Virtex-5 xc5vlx50-1ff324 FPGA device, it consumes 84 slices, provides 379.78 MHz maximum frequency, and 506.37 Mbps of throughput. Dynamic power consumption is 36.57 mW, energy 57.95 nJ, and energy/bit is 0.91 nJ/bit. In comparison to an exiting architecture, the proposed architecture provides improved performance. Further, an ASIC implementation of the architecture is done in SCL 180 nm technology for its usage as an intellectual-property (IP) core for SoCs. Gate count of the ASIC implementation is 1785 GE, area 1.55 mm 2 , and it can be operated up to 448 MHz clock frequency.