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Impact of Intrinsic Capacitances on the Dynamic Performance of Printed Electrolyte-Gated Inorganic Field Effect Transistors

Electrolyte-gated, printed field-effect transistors exhibit high charge carrier densities in the channel and thus high on-currents at low operating voltages, allowing for the low-power operation of such devices. This behavior is due to the high area-specific capacitance of the device, in which the e...

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Bibliographic Details
Published in:IEEE transactions on electron devices 2019-08, Vol.66 (8), p.3365-3370
Main Authors: Feng, Xiaowei, Punckt, Christian, Marques, Gabriel Cadilha, Hefenbrock, Michael, Tahoori, Mehdi B., Aghassi-Hagmann, Jasmin
Format: Article
Language:English
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Summary:Electrolyte-gated, printed field-effect transistors exhibit high charge carrier densities in the channel and thus high on-currents at low operating voltages, allowing for the low-power operation of such devices. This behavior is due to the high area-specific capacitance of the device, in which the electrolyte takes the role of the dielectric layer of classical architectures. In this paper, we investigate intrinsic double-layer capacitances of ink-jet printed electrolyte-gated inorganic field-effect transistors in both in-plane and top-gate architectures by means of voltage-dependent impedance spectroscopy. By comparison with deembedding structures, we separate the intrinsic properties of the double-layer capacitance at the transistor channel from parasitic effects and deduce accurate estimates for the double-layer capacitance based on an equivalent circuit fitting. Based on these results, we have performed simulations of the electrolyte cutoff frequency as a function of electrolyte and gate resistances, showing that the top-gate architecture has the potential to reach the kilohertz regime with proper optimization of materials and printing process. Our findings additionally enable accurate modeling of the frequency-dependent capacitance of electrolyte/ion gel-gated devices as required in the small-signal analysis in the circuit simulation.
ISSN:0018-9383
1557-9646
DOI:10.1109/TED.2019.2919933