Memristive Logic in Crossbar Memory Arrays: Variability-Aware Design for Higher Reliability

The advent of the first TiO 2 -based memristor in 2008 revived the scientific interest both from academia and industry for this device technology and has so far led to several emerging applications including logic and in-memory computing. Several memristive logic families have been proposed in the c...

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Bibliographic Details
Published in:IEEE transactions on nanotechnology 2019, Vol.18, p.635-646
Main Authors: Escudero, Manuel, Vourkas, Ioannis, Rubio, Antonio, Moll, Francesc
Format: Article
Language:English
Subjects:
Circuits integrats
CMOS
CNIMP
Components electrònics
Computation
Crossbar array
Enginyeria electrònica
IMPLY
In-memory computing
Integrated circuits
Logic
Logic arrays
Logic gates
MAGIC
Memristor
Memristors
Metal oxide semiconductors
Microelectrònica
Parasitics (electronics)
Performance evaluation
Ratioed logic
Resistance
Resistive switching
Switches
Switching
Titanium dioxide
Transistors
Àrees temàtiques de la UPC
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Summary:The advent of the first TiO 2 -based memristor in 2008 revived the scientific interest both from academia and industry for this device technology and has so far led to several emerging applications including logic and in-memory computing. Several memristive logic families have been proposed in the current quest for energy-efficient future computing systems. However, the limited device endurance and variability (both cycle-to-cycle and device-to-device) are important parameters to be considered in the assessment of logic operations. In this work, we used an accurate physics-based model of a bipolar memristor (supporting parasitics of the device structure and variability of switching voltages and resistance states) and demonstrate that performance of memristor-based in-memory computations can de degraded owing to both variability and state drift impact, if such features are not properly considered in the design flow. Inspired on pseudo-NMOS ratioed logic and based upon a previous CMOS-like logic scheme, we propose a crossbar-compatible memristive ratioed logic style which is tolerant to device variability and does not affect device endurance as computations do not involve conditional switching of memristors. Using the Cadence Virtuoso suite, we compare this logic scheme with MAGIC and CNIMP approaches, focusing on the universal NOR gate and more complex logic functions.
ISSN:1536-125X
1941-0085
DOI:10.1109/TNANO.2019.2923731