High Performance Accelerator for CNN Applications

The continuing advancement of the neural networks based techniques led to their exploitation in many applications, such as computer vision and the natural language processing systems where they provide high accuracy results at the cost of their high computational complexity. Hardware implemented AI...

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Bibliographic Details
Main Authors: Kyriakos, Angelos, Kitsakis, Vasileios, Louropoulos, Alexandros, Papatheofanous, Elissaios-Alexios, Patronas, Ioannis, Reisis, Dionysios
Format: Conference Proceeding
Language:English
Subjects:
Accelerator
CNN
Computer architecture
Convolution
Field programmable gate arrays
FPGA
Kernel
Mathematical model
Microsoft Windows
Parallel Processing
Registers
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Summary:The continuing advancement of the neural networks based techniques led to their exploitation in many applications, such as computer vision and the natural language processing systems where they provide high accuracy results at the cost of their high computational complexity. Hardware implemented AI accelerators provide the needed performance improvement for applications in specific areas, including robotics, autonomous systems and internet of things. The current study presents an FPGA based accelerator for Convolutional Neural Networks (CNN). The CNN model is trained for the MNIST dataset and the VHDL design targets high throughput, low power while using only on chip memory. The architecture uses parallel computations at the convolutional and fully connected layers and it has a highly pipelined output layer. The architecture implementation on a Xilinx Virtex VC707 validates the results.
ISSN:2643-3222
DOI:10.1109/PATMOS.2019.8862166