Optimizing the flattened test-generation model for very large designs

Design and test tools, such as automatic test-pattern generators (ATPG) and fault-simulators, work on a "flattened" simulation model of the entire design. Run-time performance is directly influenced by the number and complexity of simulation primitives in the flattened model. Moreover, the...

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Bibliographic Details
Main Authors: Wohl, P., Waicukauski, J.
Format: Conference Proceeding
Language:English
Subjects:
Automatic test pattern generation
Automatic testing
Computational modeling
Computer simulation
Costs
Design optimization
Discrete event simulation
Memory management
Runtime
Switches
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Summary:Design and test tools, such as automatic test-pattern generators (ATPG) and fault-simulators, work on a "flattened" simulation model of the entire design. Run-time performance is directly influenced by the number and complexity of simulation primitives in the flattened model. Moreover, the memory required to flatten and store the simulation model of current multi-million-gate designs may exceed the available address space of 32 bit computers. We present several model-optimization techniques that significantly reduce the number of simulation primitives and the associated memory usage while still preserving a complete, highly efficient flattened model. A commercial ATPG product implementing these techniques demonstrates fast simulation model construction for very large designs using a relatively small memory space.
ISSN:1089-3539
2378-2250
DOI:10.1109/TEST.2000.894263