Concurrent Irrevocability in Best-Effort Hardware Transactional Memory

• Published in: IEEE transactions on parallel and distributed systems 2020-06, Vol.31 (6), p.1301-1315
• Main Authors: Titos-Gil, Ruben, Fernandez-Pascual, Ricardo, Ros, Alberto, Acacio, Manuel E.
• Format: Article
• Language: English
• Subjects: Benchmark testing; Concurrency; Concurrency control; Concurrent computing; Hardware; multicore architectures; Parallel programming; Performance degradation; Proposals; Software; Synchronism; Synchronization; transactional memory
• ISSN: 1045-9219; 1558-2183
• DOI: 10.1109/TPDS.2019.2963030

Existing best-effort requester-wins implementations of transactional memory must resort to non-speculative execution to provide forward progress in the presence of transactions that exceed hardware capacity, experience page faults or suffer high-contention leading to livelocks. Current approaches to irrevocability employ lock-based synchronization to achieve mutual exclusion when executing a transaction non-speculatively, conservatively precluding concurrency with any other transactions in order to guarantee atomicity at the cost of degrading performance. In this article, we propose a new form of concurrent irrevocability whose goal is to minimize the loss of concurrency paid when transactions resort to irrevocability to complete. By enabling optimistic concurrency control also during non-speculative execution of a transaction, our proposal allows for higher parallelism than existing schemes. We describe the extensions to the instruction set to provide concurrent irrevocable transactions as well as the architectural extensions required to realize them on a best-effort HTM system without requiring any modification to the cache coherence protocol. Our evaluation shows that our proposal achieves an average reduction of 12.5 percent in execution time across the STAMP benchmarks, with 15.8 percent on average for highly contended workloads.