A Catalog and In-Hardware Evaluation of Open-Source Drop-In Compatible RISC-V Softcore Processors

• Main Authors: Heinz, Carsten, Lavan, Yannick, Hofmann, Jaco, Koch, Andreas
• Format: Conference Proceeding
• Language: English
• Subjects: FPGA; RISC-V; soft-core
• ISSN: 2640-0472
• DOI: 10.1109/ReConFig48160.2019.8994796

With the increasing popularity of RISC-V in the academic and industrial world, an ever growing number of open-source implementations of the instruction set have become available. However, it is not an easy task to compare the cores to one another, as they employ different interconnects, build systems and so on. This work presents an open-source catalog of RISC-V cores for use on FPGAs. All of these cores have been wrapped as drop-in compatible processing elements and can be used either standalone, or integrated into the TaPaSCo SoC composition framework. By using TaPaSCo, details of the bitstream generation flow and user-space interfaces are abstracted away, allowing the user to focus on the needs of the concrete applications when exploring the RISC-V landscape. All of the catalog's cores have been synthesized for a number of hardware platforms, and are evaluated against each other using state-of-the-art embedded processor benchmarks such as Dhrystone, Embench and CoreMark. The results show that the cores have a huge degree in performance variability. The slowest cores achieve less than 100 MHz on large UltraScale+ devices, while better FPGA-optimized cores run in excess of 500 MHz. Accordingly, the benchmarks show a wide spread of performance ranging from less than 0.5 CoreMark/MHz up to over 2.5 CoreMark/MHz.