A bit-serial implementation of the international data encryption algorithm IDEA

A high-performance implementation of the International Data Encryption Algorithm (IDEA) is presented in this paper. Using a novel bit-serial architecture to perform multiplication modulo 2/sup 16/+1, the implementation occupies a minimal amount of hardware. The bit-serial architecture enabled the al...

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Bibliographic Details
Main Authors: Leong, M.P., Cheung, O.Y.H., Tsoi, K.H., Leong, P.H.W.
Format: Conference Proceeding
Language:English
Subjects:
Asynchronous transfer mode
Clocks
Computer architecture
Computer science
Cryptography
Hardware
High-speed networks
Software performance
Throughput
Very large scale integration
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Summary:A high-performance implementation of the International Data Encryption Algorithm (IDEA) is presented in this paper. Using a novel bit-serial architecture to perform multiplication modulo 2/sup 16/+1, the implementation occupies a minimal amount of hardware. The bit-serial architecture enabled the algorithm to be deeply pipelined to achieve a system clock rate of 125 MHz on a Xilinx Virtex XCV300-6, delivering a throughput of 500 Mb/sec. With a XCV1000-6 device, the estimated performance is 2 Gb/sec, three orders of magnitude faster than a software implementation on a 450 MHz Intel Pentium II. This design is suitable for applications in on-line encryption for high-speed networks.
DOI:10.1109/FPGA.2000.903399