A Fully Integrated Reprogrammable CMOS-RRAM Compute-in-Memory Coprocessor for Neuromorphic Applications

• Published in: IEEE journal on exploratory solid-state computational devices and circuits 2020-06, Vol.6 (1), p.36-44
• Main Authors: Correll, Justin M., Bothra, Vishishtha, Cai, Fuxi, Lim, Yong, Lee, Seung Hwan, Lee, Seungjong, Lu, Wei D., Zhang, Zhengya, Flynn, Michael P.
• Format: Article
• Language: English
• Subjects: ADC; Algorithms; analog; Analog circuits; Artificial intelligence; Circuits; CMOS; compute-in-memory; Coprocessors; DAC; Distance learning; Hardware; Instruction sets (computers); Integrated circuits; Machine learning; Mathematical analysis; Matrix algebra; Matrix methods; Memory devices; Microprocessors; Power consumption; Prototypes; Random access memory; Reduced instruction set computing; Registers; resistive random access memory (RRAM); RISC; Signal processing; vector-matrix multiplication (VMM); Virtual machine monitors
• ISSN: 2329-9231; 2329-9231
• DOI: 10.1109/JXCDC.2020.2992228

Analog compute-in-memory with resistive random access memory (RRAM) devices promises to overcome the data movement bottleneck in data-intensive artificial intelligence (AI) and machine learning. RRAM crossbar arrays improve the efficiency of vector-matrix multiplications (VMMs), which is a vital operation in these applications. The prototype IC is the first complete, fully integrated analog-RRAM CMOS coprocessor. This article focuses on the digital and analog circuitry that supports efficient and flexible RRAM-based computation. A passive 54\times108 RRAM crossbar array performs VMM in the analog domain. Specialized mixed-signal circuits stimulate and read the outputs of the RRAM crossbar. The single-chip CMOS prototype includes a reduced instruction set computer (RISC) processor interfaced to a memory-mapped mixed-signal core. In the mixed-signal core, ADCs and DACs interface with the passive RRAM crossbar. The RISC processor controls the mixed-signal circuits and the algorithm data path. The system is fully programmable and supports forward and backward propagation. As proof of concept, a fully integrated 0.18- \mu \text{m} CMOS prototype with a postprocessed RRAM array demonstrates several key functions of machine learning, including online learning. The mixed-signal core consumes 64 mW at an operating frequency of 148 MHz. The total system power consumption considering the mixed-signal circuitry, the digital processor, and the passive RRAM array is 307 mW. The maximum theoretical throughput is 2.6 GOPS at an efficiency of 8.5 GOPS/W.