DRAMbulism: Balancing Performance and Predictability through Dynamic Pipelining

Worst-case execution bounds for real-time programs are profoundly impacted by the latency of accessing hardware shared resources, such as off-chip DRAM. While many different memory controller designs have been proposed in the literature, there is a trade-off between average-case performance and pred...

Full description

Saved in:
Bibliographic Details
Main Authors: Mirosanlou, Reza, Hassan, Mohamed, Pellizzoni, Rodolfo
Format: Conference Proceeding
Language:English
Subjects:
Hardware
Pipeline processing
Random access memory
Real-time systems
Schedules
Online Access:Request full text
Tags: Add Tag
No Tags, Be the first to tag this record!
Description
Summary:Worst-case execution bounds for real-time programs are profoundly impacted by the latency of accessing hardware shared resources, such as off-chip DRAM. While many different memory controller designs have been proposed in the literature, there is a trade-off between average-case performance and predictable worst-case bounds, as techniques targeted at improving the former can harm the latter and vice-versa. We find that taking advantage of pipelining between different commands can improve both, but incorporating pipelining effects in worst-case analysis is challenging. In this work, we introduce a novel DRAM controller that successfully balances performance and predictability by employing a dynamic pipelining scheme. We show that the schedule of DRAM commands is akin to a two-stage two-mode pipeline, and hence, design an easily-implementable admission rule that allows us to dynamically add requests to the pipeline without hurting worst-case bounds.
ISSN:2642-7346
DOI:10.1109/RTAS48715.2020.00-15