Slow and Steady: Measuring and Tuning Multicore Interference

• Main Authors: Iorga, Dan, Sorensen, Tyler, Wickerson, John, Donaldson, Alastair F.
• Format: Conference Proceeding
• Language: English
• Subjects: Benchmark testing; Computer architecture; Interference; Multicore processing; Program processors; Semiconductor device measurement; Software systems
• ISSN: 2642-7346
• DOI: 10.1109/RTAS48715.2020.000-6

Now ubiquitous, multicore processors provide replicated compute cores that allow independent programs to run in parallel. However, shared resources, such as last-level caches, can cause otherwise-independent programs to interfere with one another, leading to significant and unpredictable effects on their execution time. Indeed, prior work has shown that specially crafted enemy programs can cause software systems of interest to experience orders-of-magnitude slowdowns when both are run in parallel on a multicore processor. This undermines the suitability of these processors for tasks that have real-time constraints. In this work, we explore the design and evaluation of techniques for empirically testing interference using enemy programs, with an eye towards reliability (how reproducible the interference results are) and portability (how interference testing can be effective across chips). We first show that different methods of measurement yield significantly different magnitudes of, and variation in, observed interference effects when applied to an enemy process that was shown to be particularly effective in prior work. We propose a method of measurement based on percentiles and confidence intervals, and show that it provides both competitive and reproducible observations. The reliability of our measurements allows us to explore auto-tuning, where enemy programs are further specialised per architecture. We evaluate three different tuning approaches (random search, simulated annealing, and Bayesian optimisation) on five different multicore chips, spanning x86 and ARM architectures. To show that our tuned enemy programs generalise to applications, we evaluate the slowdowns caused by our approach on the AutoBench and CoreMark benchmark suites. Our method achieves a statistically larger slowdown compared to prior work in 35 out of 105 benchmarldchip combinations, with a maximum difference of 3.8\times. We envision that empirical approaches, such as ours, will be valuable for 'first pass' evaluations when investigating which multicore processors are suitable for real-time tasks.