Simulation of Total Ionizing Dose (TID) Effects Mitigation Technique for 22 nm Fully-Depleted Silicon-on-Insulator (FDSOI) Transistor

Based on 22 nm ultrathin-body fully depleted silicon-on-insulator (UTB-FDSOI) transistors, we propose a novel structure of buried insulator layer aiming at total ionizing dose (TID) effects mitigation. Using technology computer-aided design (TCAD) tools, we focus on the influences of UTB-FDSOI devic...

Full description

Saved in:
Bibliographic Details
Published in:IEEE access 2020, Vol.8, p.154898-154905
Main Authors: Yan, Gangping, Bi, Jinshun, Xu, Gaobo, Xi, Kai, Li, Bo, Fan, Linjie, Yin, Huaxiang
Format: Article
Language:English
Subjects:
Buried structures
CAD
Charge distribution
Computer aided design
Depletion
Electron traps
Irradiation
Leakage current
Leakage currents
mitigation
MOS devices
N-type semiconductors
Nitrides
Optimization
Performance evaluation
Semiconductor devices
Silicon
Silicon-on-insulator
SOI (semiconductors)
TCAD
Thickness
Threshold voltage
TID effect
Total ionizing dose
Transistors
Trapped charge
UTB-FDSOI
Citations: Items that this one cites
Items that cite this one
Online Access:Get full text
Tags: Add Tag
No Tags, Be the first to tag this record!
Description
Summary:Based on 22 nm ultrathin-body fully depleted silicon-on-insulator (UTB-FDSOI) transistors, we propose a novel structure of buried insulator layer aiming at total ionizing dose (TID) effects mitigation. Using technology computer-aided design (TCAD) tools, we focus on the influences of UTB-FDSOI devices with different structures and parameters on TID effects, such as buried oxide (BOX) layer thickness, buried Si 3 N 4 layer, and electron traps. First, we construct four types of UTB-FDSOI N-type metal-oxide semiconductor (NMOS) devices numerically, in which the novel device features a buried silicon-oxidenitride-oxide-silicon (SONOS) structure. Then, the transfer characteristics and trapped charge distribution of these devices are studied under different irradiation doses. It is known that a thinner BOX layer could lead to slighter TID effects, and the buried nitride layer and the electron traps could reduce the TID-induced leakage current (I off ). Employing these optimization structures for TID effects hardness, the innovative transistor shows much better resistance against TID effects compared to the conventional FDSOI transistors. In addition, the threshold voltage of the novel device could be increased by applying appropriate bias conditions, similar to those of programming SONOS memory, so that the Ioff caused by TID irradiation further decreases. These results provide useful guidance for designers to achieve TID effects mitigation of SOI devices.
ISSN:2169-3536
2169-3536
DOI:10.1109/ACCESS.2020.3018714