A Convolutional Neural Network Accelerator Architecture with Fine-Granular Mixed Precision Configurability

• Main Authors: Zhou, Xian, Zhang, Li, Guo, Chuliang, Yin, Xunzhao, Zhuo, Cheng
• Format: Conference Proceeding
• Language: English
• Subjects: Accelerator architectures; Arrays; Convolutional neural networks; Indexes; Registers
• ISSN: 2158-1525; 2158-1525
• DOI: 10.1109/ISCAS45731.2020.9180844

Convolutional neural networks (CNNs) have been widely deployed in deep learning applications, especially on power hungry GP-GPUs. Recent efforts in designing CNN accelerators are considered as a promising alternative to achieve higher energy efficiency. Unfortunately, with the growing complexity of CNN, the demanded computational and storage resources for accelerators keep increasing, hindering its wider applications in mobile devices. On the other hand, many quantization algorithms have been proposed for efficient CNN training, which brings many small or zero weights. This is a unique opportunity for accelerator designers to employ much fewer bits, e.g., 4 bits, in both arithmetic core and storage, thereby saving significant design cost. However, such a single precision strategy inevitably compromises the accuracy as some key operations may demand a higher precision. Thus, this paper proposes a low power CNN accelerator architecture that can simultaneously conduct computations with mixed precisions and assign the appropriate arithmetic cores to operation with different precision demands. This proposed architecture can achieve significant area and energy savings, without accuracy compromise. The experimental results show that the proposed architecture implemented on FPGA can reduces almost half of the weight storage and MAC area, and lower the dynamic power by 12.1% when compared with a state-of-the-art CNN accelerator design.