SRAM Security and Vulnerability To Hardware Trojan: Design Considerations

In this paper, we explore vulnerabilities of different blocks found in Static-Random-Access Memories (SRAMs), including core cells, sense amplifiers, replica logic, and timing unit to hardware Trojans. We discuss SRAM design and layout in detail to explore how free dead space can be exploited for ha...

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Bibliographic Details
Main Authors: Saeidi, Roghayeh, Nabavi, Morteza, Savaria, Yvon
Format: Conference Proceeding
Language:English
Subjects:
Built-in self-test
Decoding
Hardware
Layout
SRAM cells
Trojan horses
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Description
Summary:In this paper, we explore vulnerabilities of different blocks found in Static-Random-Access Memories (SRAMs), including core cells, sense amplifiers, replica logic, and timing unit to hardware Trojans. We discuss SRAM design and layout in detail to explore how free dead space can be exploited for hardware Trojan insertion. SRAM block contains some possible rare signals that can be used to trigger the deliberately inserted Trojans. The data patterns and address sequences combined with the impossible data background of conventional test can make a rare trigger condition. This paper can help designers be aware of these possible vulnerabilities and consider security requirements at the design and test stages.
ISSN:1558-3899
DOI:10.1109/MWSCAS48704.2020.9184545