Analysis and Design of a 20-MHz Bandwidth Continuous-Time Delta-Sigma Modulator With Time-Interleaved Virtual-Ground-Switched FIR Feedback

We present the design principles and circuit details of a single-bit continuous-time delta-sigma ADC that achieves 13.3-bit resolution over a 20-MHz signal bandwidth. The modulator, which operates at a sampling rate of 2.56 GHz in a 65-nm CMOS process, uses a 2 \times time-interleaved ADC to addres...

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Bibliographic Details
Published in:IEEE journal of solid-state circuits 2021-03, Vol.56 (3), p.729-738
Main Authors: Baluni, Alok, Pavan, Shanthi
Format: Article
Language:English
Subjects:
Bandwidth
Circuit design
Clocks
CMOS
Digital to analog converters
Feedback
Finite impulse response filters
FIR DAC
foreground calibration
interleaving
Jitter
Modulation
oversampling
poly-phase decimator
Resistance
virtual-ground switching
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